A model for leakage control by MOS transistlor stacking

Prevailing CMOS design practice has been very conservative with regard t o choice of transistor threshold voltage, so as t o avoid the difficult problems of threshold variations and high leakage currclnts. I t is becoming necessary t o scale threshold voltages more aggress~vely in order t o obtain further power reduction, performance improven~ent, and integration density. Substantial leakage reduction can be achi~ved in single V t designs by stacking low \.'t transistors. We have derived a simplified theoretical model which predicts the quiescent leakage current and the worst case time required t o settle t o quiescent levels in a single stack of transistors. This model can be used in a design environment t o make quick estimation of leakage with respect t o design changes. Model results are compared t o circuit sirnulation. Leakage current predictions were found t o rnatch simulation results very closely for a wide random selection of design parameter values and temperatures. Transistor stacks with mt~ltiple transistors turned off were found t o have anywhere from 2 t o 30 times lower leakage current than stack with only one transistor turned off. The time requirecl for a transistor stack t o settle t o quiescent current levels varied from a few microseconds up t o tens of milliseconds.